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1. general description the 74lv165-q100 is an 8-bit parallel-load or serial-in shift register with complementary serial outputs (q7 and q7 ) available from the last stage. when the parallel-load input (pl ) is low, parallel data from the inputs d0 to d7 are loaded into the register asynchronously. when input pl is high, data enters the register seria lly at the input ds. it shifts one place to the right (q0 ?? q1 ?? q2, etc.) with each positive-going clock transition. this feature allows parallel-to-serial converter expansion by tying the ou tput q7 to the input ds of the succeeding stage. the clock input is a gate-or structure which allows one input to be used as an active low clock enable input (ce ) input. the pin assignment for the inputs cp and ce is arbitrary and can be reversed for layout co nvenience. the low-to-high transition of the input ce should only take place while cp high fo r predictable operation. either the cp or the ce should be high before the low-to-high transition of pl to prevent shifting the data when pl is activated. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply voltage range from 1.0 v to 5.5 v ? synchronous parallel-to-serial applications ? optimized for low voltage applications: 1.0 v to 3.6 v ? synchronous serial input for easy expansion ? latch-up performance exceeds 250 ma ? 5.5 v tolerant inputs/outputs ? direct interface with ttl levels (2.7 v to 3.6 v) ? power-down mode ? complies with jedec standards: ? jesd8-5 (2.3 v to 2.7 v) ? jesd8b/jesd36 (2.7 v to 3.6 v) ? jesd8-1a (4.5 v to 5.5 v) ? esd protection: ? mil-std-833, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) 74lv165-q100 8-bit parallel-in/seria l-out shift register rev. 2 ? 24 february 2014 product data sheet
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 2 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74LV165D-Q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74lv165pw-q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 fig 1. logic symbol fig 2. iec logic symbol pqd ' ' ' ' ' ' ' ' &3 &( '6 4 4 3/ ddd ? & &>/2$'@ *>6+,)7@ ' ' ' 65* fig 3. functional diagram ddd %,76+,)75(*,67(5 3$5$//(/,16(5,$/287 3/ '6 &3 4 ' ' ' ' ' ' ' ' 4 &(
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 3 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register fig 4. logic diagram ' ' )) 4 &3 6' 5' 3/ '6 &( &3 ' )) 4 &3 6' 5' ' ' )) 4 &3 6' 5' ' ' )) 4 &3 6' 5' ' ' )) 4 &3 6' 5' ' ' )) 4 &3 6' 5' ' ' ' )) 4 &3 6' 5' ' )) 4 4 4 4 &3 6' 5' ddd '
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 4 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register 5. pinning information 5.1 pinning 5.2 pin description fig 5. pin configuration (so16 and tssop16) /94 3 / 9 && & 3 &( ' ' ' ' ' ' ' ' 4 '6 *1' 4 ddd table 2. pin description symbol pin description pl 1 parallel enable input (active low) cp 2 clock input (low-to-high edge-triggered) q7 7 complementary serial output from the last stage gnd 8 ground (0 v) q7 9 serial output from the last stage ds 10 serial data input d0 to d7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs ce 15 clock enable input (active low) v cc 16 positive supply voltage
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 5 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register 6. functional description [1] h = high voltage level; h = high voltage level one set-up time prior to the low-to-high clock transition; l = low voltage level; l = low voltage level one set-up time prio r to the low-to-high clock transition; q = state of the referenced output one set-up time prior to the low-to-high clock transition; x = don?t care; ? = low-to-high clock transition. table 3. function table [1] operating modes inputs qn registers output pl ce cp ds d0 to d7 q0 q1 to q6 q7 q7 parallel load l x x x l l l to l l h l xxxh h h to h h l serial shift h l ? l x l q0 to q5 q6 q6 hl ? h x h q0 to q5 q6 q6 hold ?do nothing? h h x x x q0 q1 to q6 q7 q7 fig 6. timing diagram &( &3 '6 3/ ' ' ' ' ' ' ' ' 4 4 pqd lqklelw vhuldovkliw ordg
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 6 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] p tot derates linearly with 8 mw/k above 70 ? c. [3] p tot derates linearly with 5.5 mw/k above 60 ? c. 8. recommended operating conditions table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v) [1] symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7 v i ik input clamping current v i < ? 0.5 v or v i >v cc +0.5v - 20 ma v i input voltage ? 0.5 +7 v i ok output clamping current v o >v cc or v o < 0 - ? 50 ma i o output current ? 0.5 v < v o < v cc +0.5v - ? 25 ma i cc supply current - +50 ma i gnd ground current ? 50 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c so16 package [2] - 500 mw tssop16 package [3] - 400 mw table 5. recommended operating conditions voltages are referenced to gnd (ground = 0 v) symbol parameter conditions min typ max unit v cc supply voltage 1.0 3.3 5.5 v v i input voltage 0 - v cc v v o output voltage 0 - v cc v t amb ambient temperature ? 40 - +85 ?c ? t/ ? v input transition rise and fall rate v cc = 1.0 v to 2.0 v 0 - 500 ns/v v cc = 2.0 v to 2.7 v 0 - 200 ns/v v cc = 2.7 v to 3.6 v 0 - 100 ns/v v cc = 3.6 v to 5.5 v 0 - 50 ns/v
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 7 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register 9. static characteristics [1] typical values are measured at t amb = 25 ? c. table 6. static characteristics at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ?c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max v ih high-level input voltage v cc = 1.2 v 0.9 - - 0.9 - v v cc = 2.3 v to 2.7 v 1.4 - - 1.4 - v v cc = 2.7 v to 3.6 v 2.0 - - 2.0 - v v cc = 4.5 v to 5.5 v 0.7v cc - - 0.7v cc -v v il low-level input voltage v cc = 1.2 v - - 0.3 - 0.3 v v cc = 2.3 v to 2.7 v - - 0.6 - 0.6 v v cc = 2.7 v to 3.6 v - - 0.8 - 0.8 v v cc = 4.5 v to 5.5 v - - 0.3v cc -0.3v cc v oh high-level output voltage v i = v ih or v il ; i o = ? 100 ? a v cc = 1.2 v - 1.2 - v cc = 2.0 v 1.8 2.0 - 1.8 - v v cc = 2.7 v 2.5 2.7 - 2.5 - v v cc = 3.0 v 2.8 3.0 - 2.8 - v v cc = 4.5 v 4.3 4.5 - 4.3 - v standard outputs: v i = v ih or v il v cc = 3.0 v; i o = ? 6 ma 2.40 2.82 - 2.20 - v v cc = 4.5 v; i o = ? 12 ma 3.60 4.20 - 3.50 - v v ol low-level output voltage v i = v ih or v il ; i o = 100 ? a v cc = 1.2v -0--- v cc = 2.0 v - 0 0.2 1.8 0.2 v v cc = 2.7 v - 0 0.2 2.5 0.2 v v cc = 3.0 v - 0 0.2 2.8 0.2 v v cc = 4.5 v - 0 0.2 4.3 0.2 v standard outputs: v i = v ih or v il v cc = 3.0 v; i o = 6 ma - 0.25 0.40 - 0.50 v v cc = 4.5 v; i o = 12 ma - 0.35 0.55 - 0.65 v i i input leakage current v i = v cc or gnd; v cc =5.5v - - ? 1- ? 1 ? a i cc supply current v i = v cc or gnd; i o =0a; v cc =5.5v - - 20 - 160 ? a ? i cc additional supply current vi = v cc ? 0.6 v; v cc = 2.7 v to 3.6 v --500-850 ? a c i input capacitance -3.5- pf
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 8 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register 10. dynamic characteristics table 7. dynamic characteristics gnd (ground = 0 v); fo r test circuit, see figure 12 symbol parameter conditions ? 40 ?c to +85 ?c ? 40 ? c to +125 ? c unit min typ [1] max min max t pd propagation delay ce , cp to q7, q7 ; see figure 7 and figure 8 [2] v cc = 1.2 v - 115 - - - ns v cc = 2.0 v - 38 61 - 76 ns v cc = 2.7 v - 27 43 - 54 ns v cc = 3.0 v to 3.6 v [3] -2236 - 45ns v cc = 3.3 v; c l = 15 pf - 18 - - - ns v cc = 4.5 v to 5.5 v [4] -1524 - 30ns pl to q7, q7 ; see figure 8 v cc = 1.2 v - 110 - - - ns v cc = 2.0 v - 35 56 - 70 ns v cc = 2.7 v - 24 39 - 49 ns v cc = 3.0 v to 3.6 v [3] -2033 - 41ns v cc = 3.3 v; c l = 15 pf - 18 - - - ns v cc = 4.5 v to 5.5 v [4] -1422 - 27ns d7 to q7, q7 ; cl = 15 pf; see figure 9 v cc = 1.2 v - 90 - - - ns v cc = 2.0 v - 28 45 - 56 ns v cc = 2.7 v - 20 32 - 40 ns v cc = 3.0 v to 3.6 v [3] -1727 - 33ns v cc = 3.3 v; c l = 15 pf - 14 - - - ns v cc = 4.5 v to 5.5 v [4] -1118 - 22ns t w pulse width cp input high to low; see figure 7 v cc = 2.0 v 34 10 - 41 - ns v cc = 2.7 v 25 8 - 30 - ns v cc = 3.0 v to 3.6 v [3] 20 7 - 24 - ns v cc = 4.5 v to 5.5 v [4] 15 5 - 18 - ns pl input low; see figure 8 v cc = 2.0 v 34 10 - 41 - ns v cc = 2.7 v 25 8 - 30 - ns v cc = 3.0 v to 3.6 v [3] 20 7 - 24 - ns v cc = 4.5 v to 5.5 v [4] 15 5 - 18 - ns
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 9 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register t rec recovery time pl to cp, ce ; see figure 8 v cc = 1.2 v - 40 - - - ns v cc = 2.0 v 24 15 - 30 - ns v cc = 2.7 v 18 11 - 23 - ns v cc = 3.0 v to 3.6 v [3] 17 10 - 21 - ns v cc = 4.5 v to 5.5 v [4] 12 7 - 15 - ns t su set-up time ds to cp, ce ; see figure 10 v cc = 1.2 v - ? 8- - -ns v cc = 2.0 v +22 ? 2- +26 -ns v cc = 2.7 v +16 ? 1- +19 -ns v cc = 3.0 v to 3.6 v [3] +13 ? 1- +15 -ns v cc = 4.5 v to 5.5 v [4] 90 - 10 -ns ce to cp, cp to ce ; see figure 10 v cc = 1.2 v - 20 - - - ns v cc = 2.0 v 22 7 - 26 - ns v cc = 2.7 v 16 5 - 19 - ns v cc = 3.0 v to 3.6 v [3] 13 4 - 15 - ns v cc = 4.5 v to 5.5 v [4] 93 - 10 -ns dn to pl ; see figure 11 v cc = 1.2 v - 25 - - - ns v cc = 2.0 v 22 8 - 26 - ns v cc = 2.7 v 16 6 - 19 - ns v cc = 3.0 v to 3.6 v [3] 13 5 - 15 - ns v cc = 4.5 v to 5.5 v [4] 94 - 10 -ns t h hold time ds to cp, ce ; dn to pl ; see figure 10 and figure 11 v cc = 1.2 v - 20 - - - ns v cc = 2.0 v 22 7 - 26 - ns v cc = 2.7 v 16 5 - 19 - ns v cc = 3.0 v to 3.6 v [3] 13 4 - 15 - ns v cc = 4.5 v to 5.5 v [4] 93 - 10 -ns ce to cp, cp to ce ; see figure 10 v cc = 1.2 v - ? 30 - - - ns v cc = 2.0 v +5 ? 8- +5 -ns v cc = 2.7 v +5 ? 6- +5 -ns v cc = 3.0 v to 3.6 v [3] +5 ? 5- +5 -ns v cc = 4.5 v to 5.5 v [4] +5 ? 4- +5 -ns table 7. dynamic characteristics ?continued gnd (ground = 0 v); fo r test circuit, see figure 12 symbol parameter conditions ? 40 ?c to +85 ?c ? 40 ? c to +125 ? c unit min typ [1] max min max
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 10 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register [1] typical values are measured at t amb = 25 c. [2] t pd is the same as t phl and t plh . [3] typical values are measured at v cc = 3.3 v. [4] typical values are measured at v cc = 5.0 v. [5] c pd is used to determine the dynamic power dissipation p d = c pd ? v cc 2 ? f i + ?? (c l ? v cc 2 ? f o ) (p d in ? w), where: f i = input frequency in mhz; f o = output frequency in mhz; ? (c l ? v cc 2 ? f o ) = sum of outputs; c l = output load capacitance in pf; v cc = supply voltage in v. 11. waveforms f max maximum frequency see figure 7 v cc = 2.0 v 14 40 - 12 - mhz v cc = 2.7 v 19 60 - 16 - mhz v cc = 3.0 v to 3.6 v [3] 24 65 - 20 - mhz v cc = 3.3 v; c l = 15 pf - 78 - - - mhz v cc = 4.5 v to 5.5 v [4] 36 75 - 30 - mhz c pd power dissipation capacitance v i =gndtov cc ; v cc = 3.3 v [5] -35- pf table 7. dynamic characteristics ?continued gnd (ground = 0 v); fo r test circuit, see figure 12 symbol parameter conditions ? 40 ?c to +85 ?c ? 40 ? c to +125 ? c unit min typ [1] max min max measurement points are given in table 8 . the changing to output assumes that internal q6 is opposite state from q7. fig 7. clock pulse (cp) and clock enable (ce ) to output (q7 or q7 ) propagation delays, clock pulse width and maximum clock frequency ddd &3&(lqsxw 4ru4rxwsxw w 3+/ w 3/+ w : i pd[ 9 0 9 2+ 9 , *1' 9 2/ 9 0
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 11 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register measurement points are given in table 8 . the changing to output assumes that internal q6 is opposite state from q7. fig 8. parallel load (pl ) pulse width, parallel load to output (q7 or q7 ) propagation delays, parallel load to clock (cp) and clock enable (ce ) recovery time ddd 3/lqsxw &(&3lqsxw 4ru4rxwsxw w 3+/ w : w uhp 9 0 9 2+ 9 , *1' 9 , *1' 9 2/ 9 0 9 0 measurement points are given in table 8 . the changing to output assumes that internal q6 is opposite state from q7. fig 9. data input (dn) to output (q7 or q7 ) propagation delays when pl is low ddd 'lqsxw 4rxwsxw 4rxwsxw w 3+/ w 3+/ 9 0 9 2+ 9 , *1' 9 2+ 9 2/ 9 2/ 9 0 w 3/+ w 3/+ 9 0
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 12 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register measurement points are given in table 8 . (1) ce may change only from high-to-low while cp is low. the shaded areas indicate when the input is permitted to change for predictable output performance. fig 10. set-up and hold times ddd w k w k w vx / w vx w k w : 9 0 9 0 *1' 9 , *1' vwdeoh 9 , '6lqsxw w vx 9 0 *1' 9 , &3 &(lqsxw &3 &(lqsxw measurement points are given in table 8 . fig 11. set-up and hold times from the data inputs (dn) to the parallel load input (pl ) ddd 'q lqsxw 3/ lqsxw w vx w k 9 , *1' 9 , *1' 9 0 9 0 w vx w k 9 0 9 0 table 8. measurement points supply voltage input output v cc v m v m < 2.7 v 0.5v cc 0.5v cc 2.7 v to 3.6 v 1.5 v 1.5 v ? 4.5 v 0.5v cc 0.5v cc
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 13 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register test data is given in table 9 . definitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. v ext = external voltage for measuring switching times. fig 12. test circuit for measuring switching times 9 0 9 0 w : w : 9 9 , 9 , qhjdwlyh sxovh srvlwlyh sxovh 9 9 0 9 0 w i w u w u w i ddh 9 (;7 9 && 9 , 9 2 '87 & / 5 7 5 / 5 / * table 9. test data supply voltage input load v ext v i t r , t f c l r l t phl , t plh < 2.7 v v cc 2.5 ns 50 pf 1 k ? open 2.7 v to 3.6 v 2.7 v 2.5 ns 50 pf, 15 pf 1 k ? open ? 4.5 v v cc 2.5 ns 50 pf 1 k ? open
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 14 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register 12. package outline fig 13. package outline sot109-1 (so16) ; z 0 $ $ $ e s ' + ( / s 4 ghwdlo; ( = h f / y 0 $ $ $ \ slqlqgh[ 81,7 $ pd[ $ $ $ e s f ' ( h + ( / / s 4 = \ z y 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp lqfkhv r r ',0(16,216lqfkglphqvlrqvduhghulyhgiurpwkhruljlqdoppgl phqvlrqv 1rwh 3odvwlfruphwdosurwuxvlrqvripplqfkpd[lpxp shuvlghduhqrwlqfoxghg 627 ( 06 pp vfdoh 62sodvwlfvpdoorxwolqhsdfndjhohdgverg\zlgwkp p 627
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 15 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register fig 14. package outline sot403-1 (tssop16) 81,7 $ $ $ e s f ' ( h + ( / / s 4 = \ z y 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp r r ',0(16,216ppduhwkhruljlqdoglphqvlrqv 1rwhv 3odvwlfruphwdosurwuxvlrqvripppd[lpxpshuvlghduh qrwlqfoxghg 3odvwlflqwhuohdgsurwuxvlrqvripppd[lpxpshuvlghdu hqrwlqfoxghg 627 02 z 0 e s ' = h $ $ $ / s 4 ghwdlo; / $ + ( ( f y 0 $ ; $ \ pp vfdoh 76623sodvwlfwklqvkulqnvpdoorxwolqhsdfndjhohdgve rg\zlgwkpp 627 $ pd[ slqlqgh[
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 16 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register 13. abbreviations 14. revision history table 10. abbreviations acronym description cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes 74lv165_q100 v.2 20140224 product data sheet - 74lv165_q100 v.1 modifications: ? typo corrected in table 2 ? pin description ? 74lv165_q100 v.1 20131111 product data sheet - -
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 17 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74lv165_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 2 ? 24 february 2014 18 of 19 nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74lv165-q100 8-bit parallel- in/serial-out shift register ? nxp b.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 24 february 2014 document identifier: 74lv165_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 recommended operating conditions. . . . . . . . 6 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 17 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 contact information. . . . . . . . . . . . . . . . . . . . . 18 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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